AMD-761 datasheet(34/264 Pages) AMD

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AMD-761™ System Controller Programmer’s Interface

Chapter 2

AMD-761™ System Controller Software/BIOS Design Guide

24081D—February 2002

Preliminary Information

Programming Notes

Bit Definitions

Configuration Address Register Type 0 (I/O:0CF8)

Bit

Name

Function

Config_En

Configuration Enable

0 = PCI configuration cycles are not generated.

1 = Accesses to the Configuration Data and Address registers are converted to

configuration cycles on the PCI.

30–24

Reserved

23—16

PCI_Bus_Num

PCI Bus Number

This bit field defines which PCI bus in the system is referenced with this address. The

AMD-761™ system controller logically implements two PCI buses. The main PCI bus

normally enumerates as bus 0 and the AGP bus enumerates as bus 1.

15—11

Dev_Num

Device Number

This bit field defines which device is accessed in the system. Devices are assigned numbers

in a system by tying the device IDSEL wire to a specific PCI AD wire. The AMD-761 system

controller decodes this field and asserts the appropriate AD wire during the address phase

to select the defined device. In the AMD-761 system controller there are two “hard-wired”

device numbers for the host to PCI bridge (0b00000) and P2P bridge (0b00001).

10—8

Func_Num

Function Number

This bit field defines which function is accessed in a given device. The AMD-761 system

controller responds to function 0 only (0b000) by default. Function 1 (DDR PDL registers)

can be enabled via writing to the PCI Control register (Dev 0:F0:0x4C) as described on

page 47.

7—2

Reg_Num

This bit field defines which specific PCI register is accessed in the device and function

specified above. The register numbers for the AMD-761 system controller device 0 are

listed in Table 6, “Device 0, Function 0 Configuration Register Map,” on page 27. The

1—0

Reserved

AMD-761 Datasheet(PDF) 34 Page - Advanced Micro Devices

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