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AMD-761 Datasheet(PDF) 55 Page - Advanced Micro Devices |
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AMD-761 Datasheet(HTML) 55 Page - Advanced Micro Devices |
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55 / 264 page  Chapter 2 AMD-761™ System Controller Programmer’s Interface 43 24081D—February 2002 AMD-761™ System Controller Software/BIOS Design Guide Preliminary Information Programming Notes Bit Definitions Extended BIU Control (Dev0:F0:0x44) Bit Name Function 31–11 Reserved Reserved 15–14 Reserved Reserved 10–8 P0_WrDataDly Write Data Delay P0_WrDataDly is the time in SYSCLK periods from the launch of a SysDC WriteData command until the launch of the first data object by the processor. This value is a calculated part of the SIP stream. This value is not provided in the BIU SIP register and is thus provided here. 7-4 Reserved Reserved 3 P0_2BitPF Two Bit Times Per Frame Enable This bit enables the use of the two bit time commands on the AMD Athlon™ processor system bus. This bit must be set when connected to an AMD Athlon processor and disabled when connected to an Alpha processor. For proper operation, BIOS must not clear this bit once it has been set. 0 = Two-bit time commands disabled 1 = Two-bit time commands enabled (AMD Athlon processor only) 2–0 Reserved Reserved These bits must be written with 0 (cleared) for normal operation. |
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