AMD-761 datasheet(48/264 Pages) AMD

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AMD-761™ System Controller Programmer’s Interface

Chapter 2

AMD-761™ System Controller Software/BIOS Design Guide

24081D—February 2002

Preliminary Information

PCI Latency Timer and Header Type

Dev0:F0:0x0C

Programming Notes

Bit

Reserved

Reset

00000000

R/W

Bit

Header_Type

Reset

00000000

R/W

Bit

Lat_Timer

Reset

00000000

R/W

Bit

Reserved

Reset

00000000

R/W

Bit Definitions

PCI Latency Timer and Header type (Dev0:F0:0x0C)

Bit

Name

Function

31–24

Reserved

23–16

Header_Type

Header Type

Bit 23 is always 0, indicating that the AMD-761™ system controller is a single function device.

Bits [22:16] are 0, indicating that Type 00 configuration space header format is supported.

15–8

Lat_Timer

Latency Timer

This bit field defines the minimum amount of time in PCI clock cycles that the bus master

can retain ownership of the bus. This action is mandatory for masters that are capable of

performing a burst consisting of more than two data phases.

7–0

Reserved

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