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AMD-761 Datasheet(PDF) 38 Page - Advanced Micro Devices |
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AMD-761 Datasheet(HTML) 38 Page - Advanced Micro Devices |
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38 / 264 page ![]() 26 AMD-761™ System Controller Programmer’s Interface Chapter 2 AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Preliminary Information 2.4.2 Configuration Register Access The AMD-761 system controller implements most registers as PCI configuration registers. The x86 software executes IN and OUT instructions to I/O addresses of 0CF8 and 0CFC to access all configuration registers. These are translated by the AMD Athlon™ processor into AMD Athlon processor system bus RdBytes and WrBytes commands with the lower 24 bits of the address field containing the logical contents of the ConfigAddr register (I/O address 0CF8). The format of this register is shown in “I/O:0CF8” on page 21 and “I/O:0CF8” on page 23. Configuration accesses in the AMD-761 system controller conform to the following rules: The AMD-761 system controller is defined to be function 0 and 1, device 0; and function 0, device 1. The IDSEL pin of all external PCI devices must be wired to 1 of AD[31:13] as logically [12:11] are assigned to device 0, 1 (AMD-761 system controller). Function 1, device 0 configuration space contains only the DDR Programmable Delay Line (PDL) registers. This space is enabled only when the appropriate bit is set in the PCI Control register (see “Dev0:F0:0x4C” on page 47). Accesses to the normal reserved PCI space of function 1 yields all 1s. Accesses to function 1 are ignored when function 1 is not enabled. Device 0 accesses correspond to the host to PCI bridge registers defined in Section 2.4.3 on page 27. Device 1 accesses correspond to the PCI-to-PCI bridge registers defined in Section 2.4.5 on page 117. Access can be byte, word or DWord in length and must be naturally aligned. Northbridges are required to create type 0 and type 1 accesses as follows: If SysAdd[23:16] = 0 (Bus# = 2'h00), a type 0 config cycle is generated and PCI AD[1:0] = 2'b00. Device#, SysAdd[15:11] is decoded and asserted on PCI AD[31:11] for IDSEL. If SysAdd[23:16] != 0 (Bus# != 2'h00), a type 1 config cycle is generated and PCI AD[1:0] = 2'b01. Bus# and Device# fields are passed onto the PCI directly with no decoding. PCI AD[31:24] = 2'h00. |
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