AMD-761 datasheet(75/264 Pages) AMD

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Chapter 2

AMD-761™ System Controller Programmer’s Interface

24081D—February 2002

AMD-761™ System Controller Software/BIOS Design Guide

Preliminary Information

Programming Notes

Bypass_En

Bypass Enable

When set, the AMD-761™ system controller internally bypasses certain memory pipe

stages for optimal performance. This bit may be set only if both of the following are true:

1. System is single processor or it is two processors and only CPU0 is present, and

2. CPU clock multiplier is 4 or greater. See “Config Status” on page 74 to determine the

clock multiplier (FID).

8–7

SysDC_Out_Dly

SysDC Out Delay

This bit field specifies the number of SysClk cycles from a return of read data type SysDC

command and the start of the corresponding data.

0b00 = Reserved

0b01 = 1 clock

0b10 = 2 clocks

0b11 = 3 clocks

This field is initialized by pinstrapping during reset.

6–3

SysDC_In_Dly

SysDC In Delay

This bit field specifies the number of SysClk cycles from a write data type SysDC command

and the start of the corresponding data.

0b0000 = 1 clock

0b0001 = 2 clocks

.............................

0b1111 = 16 clocks

This field is initialized by pinstrapping during reset.

2WR2_RD

WR2 Read

This field defines the number of SysClk cycles that are inserted between write data and

read data cycles to allow the AMD Athlon™ processor system bus data wires to turn

around. This field is initialized by pinstrapping during reset.

1–0

RD2_WR

RD2 Write

This field defines the number of SysClk cycles that are inserted between read data and

write data cycles to allow the AMD Athlon processor system bus data wires to turn

around. This field is initialized by pinstrapping during reset.

Bit Definitions (Continued)

BIU0 Status/Control (Dev0:F0:0x60)

Bit

Name

Function

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