AMD-761 datasheet(83/264 Pages) AMD

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Chapter 2

AMD-761™ System Controller Programmer’s Interface

24081D—February 2002

AMD-761™ System Controller Software/BIOS Design Guide

Preliminary Information

Bit Definitions

PCI Arbitration Control (Dev0:F0:0x84)

Bit

Name

Function

31–24

AGP_VGA_BIOS

AGP VGA BIOS

These bits when set indicate that the corresponding (16-KByte) segment should be

mapped to the AGP PCI bus. Bit 24 corresponds to the addresses 0xC0000–0xC3FFF and

bit 31 maps addresses 0xDC000–0xDFFFF to the AGP PCI interface. Set one or more of

these bits if the AGP graphics card has a ROM BIOS.

Tgt_Latency

Target Latency

This bit is designed to ensure that the AMD-761™ system controller is compliant to the PCI

maximum target latency rule. Note that this compliance applies only to the PCI bus and

not the AGP bus.

0 = AMD-751™ system controller-compatible, the AMD-761 system controller does not

disconnect a master when it cannot service a read request within 32 PCI clock

periods (initial latency) or 8 clocks (subsequent data cycles).

1 = If the AMD-761 system controller cannot respond to a memory read within 32 clocks

for the initial access, or 8 clocks for each subsequent access, it forces a retry.

Note:

To prevent potential deadlocks, set this bit and clear bit 3 (Tgt_Lat_Tim_Dis) if

the system has PCI to AGP traffic.

22–18

Reserved

AGP_Chain_En

Enable AGP Chaining

When set, CPU writes to the AGP bus are chained together.

PCI_Chain_En

Enable PCI Chaining

When set, CPU writes to PCI are chained together.

MDA_Debug

MDA Debug

This bit allows monochrome display adapters (MDA) to be used simultaneously with AGP

cards for debug of AGP device drivers. The behavior of the AMD-761 system controller

display adapters is a function of this bit and the VGA Enable in (D1:0x3C[19]) as follows:

MDA address ranges:

Memory: 0B0000h–0B7FFFh

I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh

VGA = 0, MDA = 0: all MDA and VGA references go to PCI

VGA = 0, MDA = 1: operation undefined

VGA = 1, MDA = 0: all VGA references go to AGP, MDA only (I/O 3BFh) goes to PCI

VGA = 1, MDA = 1: all VGA references go to AGP, all MDA (including memory) go to PCI

PCI_WR_Post

_Rtry

PCI Write Post Retry

When set, this bit enables retries on PCI if there are pending posted writes.

AGP_WR_Post

_Rtry

AGP Write Post Retry

When set, this bit enables retries on the AGP bus if there are pending posted writes.

AMD-761 Datasheet(PDF) 83 Page - Advanced Micro Devices

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