 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AMD-761 Datasheet(PDF) 68 Page - Advanced Micro Devices |
|
|
|||||||||||||||||||||||||||||
AMD-761 Datasheet(HTML) 68 Page - Advanced Micro Devices |
|
|
68 / 264 page  56 AMD-761™ System Controller Programmer’s Interface Chapter 2 AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Preliminary Information DRAM Mode/Status Dev0:F0:0x58 Register Description This register provides general mode control and status reporting of the DRAM system. Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. 31 30 29 28 27 26 25 24 Bit Clk_Dis5 Clk_Dis4 Clk_Dis3 Clk_Dis2 Clk_Dis1 Clk_Dis0 SDRAM_Init Reserved Reset 00000000 R/W R/W R/W1S R 23 22 21 20 19 18 17 16 Bit Mode_Reg _ Status STR_Control Burst_Ref_En Ref_Dis Cyc_Per_Ref Reset 000XXXXX R/W R/W1S R/W 15 14 13 12 11 10 9 8 Bit Reserved Reset 00000000 R/W R 7 6 5 4 3 2 1 0 Bit CS7_X4Mode CS6_X4Mode CS5_X4Mode CS4_X4Mode CS3_X4Mode CS2_X4Mode CS1_X4Mode CS0_X4Mode Reset XXXXXXXX R/W R/W R/W R/W R/W R/W R/W R/W R/W |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
