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AMD-761 Datasheet(PDF) 72 Page - Advanced Micro Devices |
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AMD-761 Datasheet(HTML) 72 Page - Advanced Micro Devices |
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72 / 264 page  60 AMD-761™ System Controller Programmer’s Interface Chapter 2 AMD-761™ System Controller Software/BIOS Design Guide 24081D—February 2002 Preliminary Information Programming Notes Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This action should be done prior to attempting DRAM access. The Clk_Dis bits are cleared by RESET#, and therefore all DDR DRAM interface clock pairs are enabled when exiting the Advanced Configuration and Power Interface (ACPI) S3 sleep state (suspend to RAM). BIOS should disable any clock pairs that are connected to unpopulated DIMM slots upon exit of S3. When a chip select is programmed to operate in x4 DIMM mode, the DM[8:0] pins become DQS pins for that chip select. The pad configuration for the DM[8:0] pins is automatically controlled by the DQS_Drive field (Dev 0:F0:0x40) instead of the MDAT_Drive field, when any chip select is configured for x4 DIMM mode. |
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