AMD-761 datasheet(16/264 Pages) AMD

16 / 264 page

Overview

Chapter 1

AMD-761™ System Controller Software/BIOS Design Guide

24081D—February 2002

Preliminary Information

The AMD-761 system controller provides BIOS the ability to

override the reporting of fast write and 4X rate support. This

override function is accomplished through a write to a separate

specified as read-only in the AGP specification.

Re fer to Sec t io n 6 .2 on page 2 08 fo r de tails of this

implementation.

Interrupt Pin Control

R/W Attributes

The Int_Pin field in the AGP/PCI Interrupt and Bridge Control

to all 0s. If the BIOS is required to initialize this field to

another value, it must first change this field to R/W by setting

the Int_Pin_Cntl bit in the Miscellaneous Device 1 Control

The AMD-761 system controller does not use the Int_Pin field

internally, the register is provided for software compatibility only.

Silicon Revisions

The reader is advised to read the AMD-761™ System Controller

Revision Guide, order# 23613, for the most current information

for the version of silicon being used. The silicon revision is

available by reading the PCI revision ID and Class Code

1.1.3

Power-On Reset Initialization

All of the AMD-761 system controller’s configuration registers

must be initialized by BIOS after initial power-on, paying especially

close attention to the registers that are not initialized to a known

value.

T h e AMD-761 system c o ntr o l l er

i s r e set when t h e

Southbridge’s PCIRST# pin is asserted, which occurs when

transitioning from the Mechanical Off, S5, S4, or S3 sleep

states.

To accommodate support of the Advanced Configuration and

Powe r Int e rf ac e ( ACP I) S3 (suspend to RAM) powe r

management state, the registers listed in Table 1 on page 5 are

not initialized to a known state after reset (RESET# asserted),

and they must be initialized by BIOS after initial power-on for

proper operation. These registers retain the value programmed

by BIOS after subsequent assertions of the RESET# pin when

transitioning to and from the S3 sleep state.

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