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AMD-761™ System Controller Programmer’s Interface

Chapter 2

AMD-761™ System Controller Software/BIOS Design Guide

24081D—February 2002

Preliminary Information

Programming Notes

If the target latency bit is set (bit 23 of Dev 0:F0:0x84), then the delayed transactions enable (bit 2) must be set when the

front-side bus is clocked at 66 MHz.

When enabling PCI ordering rules compliance, it is recommended that delayed transactions be enabled simultaneously

for optimal performance.

Refer to See Chapter 5, “PCI Bus Interface” on page 195 for more information on the transaction options in the AMD-761

system controller. Refer to See Chapter 7, “Recommended BIOS Settings” on page 211 for the recommended bit settings

for these bits.

Note that the WSC_DIR pin is implemented only in silicon revisions B4 and above and must be treated as Reserved (write

a 0) in all other silicon revisions.

Bit Definitions

PCI Control (Dev0:F0:0x4C)

Bit

Name

Function

31—4

Reserved

3WSC_DIR

Write Snoop Complete Direction Control

This bit controls the direction and function of the Write Snoop Complete (WSC#) pin.

Refer to the AMD-761™ System Controller Datasheet, order# 24088, for a full description

of the WSC# pin.

0 = Bidirectional mode for use with Southbridges that drive WSC# as an output and

sample WSC# as an input (such as the AMD-766™ peripheral bus controller). In this

mode, the WSC# pin of the AMD-761 system controller defaults as an input and is

driven by the Northbridge only after the pin is first asserted by the Southbridge.

1 = Unidirectional mode for use with Southbridges that only sample WSC# as an input.

In this mode, the WSC# pin is always driven by the AMD-761 system controller.

Note: This bit is implemented only in silicon revision B4 and above. It is reserved in all

previous silicon revisions and must be cleared.

PCI_DT_En

Delayed Transactions Enable (PCI)

0 = Delayed transactions disabled on the PCI interface

1 = Delayed transactions enabled on the PCI interface

1PCI_OR_En

Ordering Rules Compliance Enable (PCI)

This bit controls how the AMD-761 system controller PCI bus interface orders transactions.

0 = PCI ordering rules compliance disabled

1 = PCI ordering rules compliance enabled

Func1_En

Function 1 Enable

This bit controls access to device 0, function 1 configuration space (DDR PDL registers).

Refer to “Device 0, Function 1: DDR PDL Configuration Registers” on page 97 for more

information on the function 1 registers.

0 = Device 0, function 1 disabled

1 = Device 0, function 1 enabled

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