AMD-761 datasheet(14/264 Pages) AMD

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Overview

Chapter 1

AMD-761™ System Controller Software/BIOS Design Guide

24081D—February 2002

Preliminary Information

1.1

General BIOS Initialization Requirements

The following sections provide general requirements for BIOS

when pr o g ra mmi ng the AMD-761 sy stem contr o l l e r

configuration registers. Note that the register descriptions also

include some specific programming notes.

1.1.1

AMD-761™ Configuration Spaces

The AMD-761 system controller contains both I/O and memory-

mapped configuration spaces as listed below.

I/O Mapped Space

•

PCI configuration space address and data (CF8h, CFCh)

•

Host bridge registers mapped in PCI configuration

space, device 0, function 0

•

DDR interface PDL and I/O controls mapped in PCI

configuration space to device 0, function 1

•

PCI to PCI bridge/AGP registers mapped in PCI

configuration space to device 1, function 0

GART Memory-Mapped Registers

•

Mapped

memory

space

defined

the

programming of Base Address 1: GART Memory Mapped

1.1.2

Special Configuration Sequencing Requirements

This section outlines a few cases in the AMD-761 system

controller configuration registers that require special handling

for proper BIOS programming.

Configuration Cycles

Enable

The AMD-761 system controller supports configuration

address space as defined by the PCI Local Bus Specification,

Revision 2.2, which defines a unique 256-byte space that is

accessed through two 32-bit index registers mapped in I/O

space.

As defined in the PCI specification, configuration cycles are

generated on the PCI bus only when bit 31 of the Configuration

Address register is set.

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