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IP175DLF Datasheet(PDF) 113 Page - List of Unclassifed Manufacturers

Part # IP175DLF
Description  5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)
PDF  145 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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IP175DLF Datasheet(HTML) 113 Page - List of Unclassifed Manufacturers

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IP175DLF
Datasheet
113/145
August 22, 2014
Copyright © 2007, IC Plus Corp.
IP175DLF-DS-R10.1
PHY
MII
ROM
R/W
Description
Default
2[5:0]
60[5:0] R/W KEEP_TAG[5:0]
(QinQ register)
Keep VLAN Tag Header
0: Disabled
1: Keep VLAN tag header from frame. If frames transmission
on a egress port tags frame, the frame may contain two tag
headers
6’h00
5.11.4
Default VLAN Information
PHY
MII
ROM
R/W
Description
Default
22
3[15:0]
62[7:0]
61[7:0]
R/W TPID_VALUE[15:0]
802.1Q Tag Protocol Type
16’h8100
PHY
MII
ROM
R/W
Description
Default
4[15:0]
64[7:0]
63[7:0]
R/W VLAN_INFO_0.
Port 0 default VLAN information value (PVID_0)
16’h0001
5[15:0]
66[7:0]
65[7:0]
R/W VLAN_INFO_1.
Port 1 default VLAN information value (PVID_1)
16’h0001
6[15:0]
68[7:0]
67[7:0]
R/W VLAN_INFO_2.
Port 2 default VLAN information value (PVID_2)
16’h0001
7[15:0]
70[7:0]
69[7:0]
R/W VLAN_INFO_3.
Port 3 default VLAN information value (PVID_3)
16’h0001
8[15:0]
72[7:0]
71[7:0]
R/W VLAN_INFO_4.
Port 4 default VALN information value (PVID_4)
16’h0001
22
9[15:0]
74[7:0]
73[7:0]
R/W VLAN_INFO_5.
Port 5 default VALN information value (PVID_5)
16’h0001



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