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TMS320F Datasheet(PDF) 104 Page - Texas Instruments |
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TMS320F Datasheet(HTML) 104 Page - Texas Instruments |
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104 / 389 page  Instruction Set Summary 7-4 ZLVC ZLVC Two 4-bit fields — each representing the following conditions: ACC = 0 Z ACC < 0 L Overflow V Carry C A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a mask field. A 1 in the corre- sponding mask bit indicates that condition is being tested. For example, to test for ACC ≥ 0, the Z and L fields are set, and the V and C fields are not set. The Z field is set to test the condi- tion ACC = 0, and the L field is reset to test the condition ACC ≥ 0.The second 4-bit field (bits 4 – 7) indicates the state of the conditions to test. The conditions possible with these eight bits are shown in the descriptions for the BCND, CC, and RETC instructions. + 1 word The second word of a 2-word opcode. This second word contains a 16-bit constant. Depending on the instruction, this constant is a long immediate value, a program memory ad- dress, or an address for an I/O port or an I/O-mapped register. |
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