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TMS320F Datasheet(PDF) 141 Page - Texas Instruments

Part # TMS320F
Description  CPU and Instruction Set
PDF  389 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F Datasheet(HTML) 141 Page - Texas Instruments

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Branch on Auxiliary Register Not Zero
BANZ
7-41
Assembly Language Instructions
Example 1
BANZ
PGM0
;(PGM0 labels program address 0)
Before Instruction
After Instruction
ARP
0
ARP
0
AR0
5h
AR0
4h
Because the content of AR0 is not zero, the program address denoted by
PGM0 is loaded into the program counter (PC), and the program continues ex-
ecuting from that location. The default auxiliary register operation is a decre-
ment of the current auxiliary register content; thus, AR0 contains 4h at the end
of the execution.
or
Before Instruction
After Instruction
ARP
0
ARP
0
AR0
0h
AR0
FFFFh
Because the content of AR0 is zero, the branch is not executed; instead, the
PC is incremented by 2, and execution continues with the instruction following
the BANZ instruction. Because of the default decrement, AR0 is decremented
by 1, becoming –1.
Example 2
MAR *,AR0
;Set ARP to point to AR0.
LAR AR1,#3
;Load AR1 with 3.
LAR AR0,#60h
;Load AR0 with 60h.
PGM191
ADD *+,AR1
;Loop: While AR1 not zero,
BANZ PGM191,*–AR0 ;add data referenced by AR0
;to accumulator and increment
;AR0 value.
The contents of data-memory locations 60h–63h are added to the accumula-
tor.



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