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TMS320F Datasheet(PDF) 199 Page - Texas Instruments

Part # TMS320F
Description  CPU and Instruction Set
PDF  389 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F Datasheet(HTML) 199 Page - Texas Instruments

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Load TREG and Subtract Previous Product
LTS
7-99
Assembly Language Instructions
Syntax
LTS
dma
Direct addressing
LTS
ind [, ARn]
Indirect addressing
Operands
dma:
7 LSBs of the data-memory address
n:
Value from 0 to 7 designating the next auxiliary register
ind:
Select one of the following seven options:
*
*+
*–
*0+
*0–
*BR0+
*BR0–
LTS
dma
15
14
13
12
11
10
987
6543
210
0
1
1
1
0
1
0
0
0
dma
LTS
ind [, ARn]
15
14
13
12
11
10
987
6543
210
0
1
1
1
0
1
0
0
1
ARU
N
NAR
Note:
ARU, N, and NAR are defined in section 6.3,
Indirect Addressing Mode (page 6-9).
Execution
Increment PC, then ...
(data-memory address)
→ TREG
ACC – shifted (PREG)
→ ACC
Status Bits
Affected by
Affects
PM and OVM
C and OV
Description
TREG is loaded with the contents of the addressed data-memory location. The
contents of the product register, shifted as defined by the contents of the PM
status bits, are subtracted from the accumulator. The result is placed in the
accumulator.
The carry bit is cleared (C = 0) if the result of the subtraction generates a
borrow, and is set (C = 1) if it does not generate a borrow.
Words
1
Cycles for a Single LTS Instruction
Program
Operand
ROM
DARAM
SARAM
External
DARAM
1
1
1
1+p
SARAM
1
1
1, 2†
1+p
External
1+d
1+d
1+d
2+d+p
† If the operand and the code are in the same SARAM block
Opcode



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