TMS320F datasheet(249/389 Pages) TI

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Store Low Accumulator With Shift

SACL

7-149

Assembly Language Instructions

Syntax

SACL

dma [, shift2 ]

Direct addressing

SACL ind [,

shift2 [, ARn] ]

Indirect addressing

Operands

dma:

7 LSBs of the data-memory address

shift2:

Left shift value from 0 to 7 (defaults to 0)

Value from 0 to 7 designating the next auxiliary register

ind:

Select one of the following seven options:

*–

*0+

*0–

*BR0+

*BR0–

SACL

dma [, shift2 ]

987

6543

210

shift2

dma

SACL

ind [ , shift 2 [ , ARn ] ]

987

6543

210

shift2

ARU

NAR

Note:

ARU, N, and NAR are defined in section 6.3,

Indirect Addressing Mode (page 6-9).

Execution

Increment PC, then ...

16 LSBs of ((ACC)

2shift2) → data-memory address

Status Bits

This instruction is not affected by SXM.

Description

The SACL instruction copies the entire accumulator into the output shifter,

where it left shifts the entire 32-bit number from 0 to 7 bits. It then copies the

lower 16 bits of the shifted value into data memory. During the shift, the

low-order bits are filled with zeros, and the high-order bits are lost. The

accumulator itself remains unaffected.

Words

Cycles for a Single SACL Instruction

Program

Operand

ROM

DARAM

SARAM

External

DARAM

1+p

SARAM

1, 2†

1+p

External

2+d

4+d+p

† If the operand and the code are in the same SARAM block.

Opcode

Cycles

TMS320F Datasheet(PDF) 249 Page - Texas Instruments

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