TMS320F datasheet(285/389 Pages) TI

285 / 389 page

Table Read

TBLR

7-185

Assembly Language Instructions

Syntax

TBLR

dma

Direct addressing

TBLR

ind [, ARn]

Indirect addressing

Operands

dma:

7 LSBs of the data-memory address

Value from 0 to 7 designating the next auxiliary register

ind:

Select one of the following seven options:

*–

*0+

*0–

*BR0+

*BR0–

TBLR

dma

987

6543

210

dma

TBLR

ind [, ARn]

987

6543

210

ARU

NAR

Note:

ARU, N, and NAR are defined in section 6.3,

Indirect Addressing Mode (page 6-9).

Execution

Increment PC, then ...

(PC)

→ MSTACK

(ACC(15:0))

→ PC

(pma)

→ data-memory address

For indirect, modify (current AR) and (ARP) as specified

(PC) + 1

→ PC

While (repeat counter)

≠ 0

(pma)

→ data-memory address

For indirect, modify (current AR) and (ARP) as specified

(PC) + 1

→ PC

(repeat counter) –1

→ repeat counter.

(MSTACK)

→ PC

Status Bits

None

Description

The TBLR instruction transfers a word from a location in program memory to

a data-memory location specified by the instruction. The program-memory ad-

dress is defined by the low-order 16 bits of the accumulator. For this operation,

a read from program memory is performed, followed by a write to data memory.

When repeated with the repeat (RPT) instruction, TBLR effectively becomes

a single-cycle instruction, and the program counter that was loaded with

(ACC(15:0)) is incremented once each cycle.

Words

Opcode

TMS320F Datasheet(PDF) 285 Page - Texas Instruments

TMS320F Datasheet(HTML) 285 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL