TMS320F datasheet(288/389 Pages) TI

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TBLW

Table Write

7-188

Syntax

TBLW

dma

Direct addressing

TBLW

ind [, ARn]

Indirect addressing

Operands

dma:

7 LSBs of the data-memory address

Value from 0 to 7 designating the next auxiliary register

ind:

Select one of the following seven options:

*–

*0+

*0–

*BR0+

*BR0–

TBLW

dma

987

6543

210

dma

TBLW

ind [, ARn]

987

6543

210

ARU

NAR

Note:

ARU, N, and NAR are defined in section 6.3,

Indirect Addressing Mode (page 6-9).

Execution

Increment PC, then ...

(PC+1)

→ MSTACK

(ACC(15:0))

→ PC+1

(data-memory address)

→ pma,

For indirect, modify (current AR) and (ARP) as specified

(PC) + 1

→ PC

While (repeat counter)

≠ 0

(data-memory address)

→ pma,

For indirect, modify (current AR) and (ARP) as specified

(PC) + 1

→ PC

(repeat counter) –1

→ repeat counter.

(MSTACK)

→ PC+1

Status Bits

None

Description

The TBLW instruction transfers a word in data memory to program memory.

The data-memory address is specified by the instruction, and the program-

memory address is specified by the lower 16 bits of the accumulator. A read

from data memory is followed by a write to program memory to complete the

instruction. When repeated with the repeat (RPT) instruction, TBLW effectively

becomes a single-cycle instruction, and the program counter that was loaded

with (ACC(15:0)) is incremented once each cycle.

Words

Opcode

TMS320F Datasheet(PDF) 288 Page - Texas Instruments

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