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VT8235 Datasheet(PDF) 101 Page - VIA Technologies, Inc. |
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VT8235 Datasheet(HTML) 101 Page - VIA Technologies, Inc. |
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101 / 145 page  VT8235 V-Link South Bridge Revision 1.22 October 24, 2002 -95- Device 17 Function 1 Enhanced IDE Controller Registers UrpuytvrÃDp XrÃ8rp IDE-Controller-Specific Configuration Registers Offset 40 - Chip Enable (00h) ...........................................RW 7-2 Reserved ........................................ always reads 0 1 Primary Channel 0 Disable .................................................. default 1 Enable 0 Secondary Channel 0 Disable .................................................. default 1 Enable Offset 41 - IDE Configuration I (00h)..............................RW 7 Primary IDE Read Prefetch Buffer 0 Disable .................................................. default 1 Enable 6 Primary IDE Post Write Buffer 0 Disable .................................................. default 1 Enable 5 Secondary IDE Read Prefetch Buffer 0 Disable .................................................. default 1 Enable 4 Secondary IDE Post Write Buffer 0 Disable .................................................. default 1 Enable 3-0 Reserved ........................................ always reads 0 Offset 42 - IDE Configuration II (00h) ............................RW 7 PIO Operating Mode - Primary Channel Selects the mode used in the primary channel for the I/O Base Address (not IRQ routing or sharing) 0 Compatibility Mode (fixed addressing). default 1 Native PCI Mode (flexible addressing) 6 PIO Operating Mode - Secondary Channel Selects the mode used in the secondary channel for the I/O Base Address (not IRQ routing or sharing) 0 Compatibility Mode (fixed addressing). default 1 Native PCI Mode (flexible addressing) 5-0 Reserved ........................................ always reads 0 Offset 43 - FIFO Configuration (0Ah) ............................ RW 7-4 Reserved ........................................always reads 0 3-2 Primary Channel FIFO Threshold Determines the threshold required before the primary channel FIFO is flushed. 00 FIFO flushed when 1/4 full 01 FIFO flushed when 1/2 full 10 FIFO flushed when 3/4 full................... default 11 FIFO flushed when completely full (32 DWs) 1-0 Secondary Channel FIFO Threshold Determines the threshold required before the secondary channel FIFO is flushed. 00 FIFO flushed when 1/4 full 01 FIFO flushed when 1/2 full 10 FIFO flushed when 3/4 full................... default 11 FIFO flushed when completely full (32 DWs) |
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