VT8235 datasheet(105/145 Pages) VIA

105 / 145 page

VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-99-

Device 17 Function 1 Enhanced IDE Controller Registers

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Offset 70 – Primary IDE Status ....................................... RO

Interrupt Status................................................... RO

Primary channel interrupt request pending

Prefetch Buffer Status ........................................ RO

PIO Prefetch transaction in progress

Post Write Buffer Status..................................... RO

PIO Post Write transaction in progress

DMA Read Prefetch Status ................................ RO

DMA Read Prefetch transaction in progress

DMA Write Pipeline Status................................ RO

DMA Write transaction in progress

S/G Operation Complete .................................... RO

Scatter / Gather operation complete

FIFO Empty Status............................................. RO

Primary Channel FIFO empty

Response to External DMA Request ................. RO

External pri channel DMA request pending

Offset 71 – Primary Interrupt Control (01h)..................RW

7-1

Reserved

........................................ always reads 0

Interrupt Gating

Disable

Enable (IRQ output gated until FIFO empty)

....................................................default

Offset 78 – Secondary IDE Status.................................... RO

Interrupt Status................................................... RO

Secondary channel interrupt request pending

Prefetch Buffer Status ........................................ RO

PIO Prefetch transaction in progress

Post Write Buffer Status..................................... RO

PIO Post Write transaction in progress

DMA Read Prefetch Status ................................ RO

DMA Read Prefetch transaction in progress

DMA Write Pipeline Status................................ RO

DMA Write transaction in progress

S/G Operation Complete .................................... RO

Scatter / Gather operation complete

FIFO Empty Status............................................. RO

Secondary Channel FIFO empty

Response to External DMA Request ................. RO

External sec channel DMA request pending

Offset 79 - Secondary Interrupt Control (01h) ...............RW

7-1

Reserved

........................................ always reads 0

Interrupt Gating

Disable

Enable (IRQ output gated until FIFO empty)

....................................................default

Offset 83-80 – Primary S/G Descriptor Address ............ RO

Offset 8B-88 – Secondary S/G Descriptor Address ........ RO

These registers are used for debugging purposes only.

IDE Power Management Registers

Offset C3-C0 – Power Management Capabilities ........... RO

31-0 PCI PM Block 1

.................always reads 0002 0001h

This

field

reports

support

details

for

Power

Management Capabilities according to the PCI Power

Management specification.

Offset C7-C4 – Power State .............................................. RO

31-2 Reserved

........................................always reads 0

1-0

Power State

00 D0

.................................................... default

01 -reserved-

10 -reserved-

11 D3 Hot

IDE Back Door Registers

Offset D0 – Back Door – Revision ID (06h) .................... RW

Offset D3-D2 – Back Door – Device ID (0571h) ............. RW

Offset D5-D4 – Back Door – Sub-Vendor ID (0000h).... RW

Offset D7-D6 – Back Door – Sub-Device ID (0000h) ..... RW

IDE Revision ID

Offset F6 – IDE New Revision ID (07h) ........................... RO

IDE I/O Registers

These registers are compliant with the SFF 8038I v1.0

standard. Refer to the SFF 8038I v1.0 specification for further

details.

I/O Offset 0 - Primary Channel Command

I/O Offset 2 - Primary Channel Status

I/O Offset 4-7 - Primary Channel PRD Table Address

I/O Offset 8 - Secondary Channel Command

I/O Offset A - Secondary Channel Status

I/O Offset C-F - Secondary Channel PRD Table Address

VT8235 Datasheet(PDF) 105 Page - VIA Technologies, Inc.

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