VT8235 datasheet(104/145 Pages) VIA

104 / 145 page

VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-98-

Device 17 Function 1 Enhanced IDE Controller Registers

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Offset 54 – UltraDMA FIFO Control (04h) ....................RW

Reserved

........................................ always reads 0

Lower ISA Request Priority When Write Device

Packet Command is Issued

The IDE secondary channel shares a bus internally

with the ISA interface. When this bit is enabled, the

IDE secondary channel is given higher priority over

ISA, which results in better performance.

Disable .................................................. default

Enable

Clear Native Mode Interrupt on Falling Edge of

Gated Interrupt

Disable .................................................. default

Enable.

The interrupt will be automatically

cleared on the falling edge of the gated

interrupt.

Improve

PIO

Prefetch

and

Post-Write

Performance

Enable.

PIO

prefetch

and

post

write

performance is increased by being given

higher throughput. ................................. default

Disable

Memory Prefetch Size

This bit determines how many lines are prefetched

from memory for IDE transactions.

Prefetch 1 line ....................................... default

Prefetch 2 lines (16 DoubleWords).

This

setting improves ATA100 throughput.

Change Drive Clears All FIFO & Internal States

Disable

Command switch from one drive to another

drive in the same channel terminates all

previous outstanding transactions involving

the previous drive. .................................default

Reserved

........................................ always reads 0

Complete DMA Cycle with Transfer Size Less

Than FIFO Size

Enable.

DMA transfer size is less than the

FIFO size ............................................... default

Disable

Offset 55 – IDE Clock Gating (00h) ................................ RW

7-2

Reserved

........................................always reads 0

Dynamic 100 / 133 MHz Clock Gating

Enable .................................................... default

Disable

Dynamic 66 MHz Clock Gating

Enable .................................................... default

Disable

Offset 61-60 - Primary Sector Size (0200h) .................... RW

15-12 Reserved

........................................always reads 0

11-0 Number of Bytes Per Sector

...def=200h (512 bytes)

This field determines the maximum number of bytes

that can be prefetched when Rx44[4] = 1.

Offset 69-68 - Secondary Sector Size (0200h)................. RW

15-12 Reserved

........................................always reads 0

11-0 Number of Bytes Per Sector

...def=200h (512 bytes)

This field determines the maximum number of bytes

that can be prefetched when Rx44[4] = 1.

VT8235 Datasheet(PDF) 104 Page - VIA Technologies, Inc.

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