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VT8235 Datasheet(PDF) 106 Page - VIA Technologies, Inc.

Part # VT8235
Description  V-LINK CLIENT HIGHLY INTEGRATED SOUTH BRIDGE
PDF  145 Pages
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Manufacturer  VIA [VIA Technologies, Inc.]
Direct Link  https://www.viatech.com/en/
Logo VIA - VIA Technologies, Inc.

VT8235 Datasheet(HTML) 106 Page - VIA Technologies, Inc.

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VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002
-100-
Device 17 Function 5 Audio Controller Registers
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Device 17 Function 5 Registers - AC97 Audio Controller
The audio controller interface is hardware compatible with
AC97.
The PCI configuration registers for the audio
controller are located in the function 5 PCI configuration
space. The I/O registers are located in the system I/O space.
PCI Configuration Space Header
Offset 1-0 - Vendor ID ...................................................... RO
7-0
Vendor ID
................. (1106h = VIA Technologies)
Offset 3-2 - Device ID ........................................................ RO
7-0
Device ID
(3059h = VT8235 Audio Controller)
Offset 5-4 - Command.......................................................RW
15-10 Reserved
........................................ always reads 0
9
Reserved
(fast back-to-back)....................... fixed at 0
8
SERR# Enable
............................................ fixed at 0
7
Reserved
(address stepping)........................ fixed at 0
6
Reserved
(parity error response) ................. fixed at 0
5
Reserved
(VGA palette snoop) ................... fixed at 0
4
Reserved
(memory write and invalidate) .... fixed at 0
3
Reserved
(special cycle monitoring) ........... fixed at 0
2
Bus Master
................................................ fixed at 0
1
Memory Space
............................................ fixed at 0
0
I/O Space
............................... default=0 (disabled)
Offset 7-6 - Status .............................................................. RO
15
Detected Parity Error
................................ fixed at 0
14
Signalled System Error
.............................. fixed at 0
13
Received Master Abort
.............................. fixed at 0
12
Received Target Abort
............................... fixed at 0
11
Signalled Target Abort
.............................. fixed at 0
10-9 DEVSEL# Timing
00 Fast
01 Medium .................................................... fixed
10 Slow
11 Reserved
8
Data Parity Error
....................................... fixed at 0
7
Fast Back-to-Back Capable
....................... fixed at 0
6-5
Reserved
........................................ always reads 0
4
PM 1.1
................................................ fixed at 1
3-0
Reserved
........................................ always reads 0
Offset 8 - Revision ID (nnh).............................................. RO
7-0
Silicon Revision Code
........................... default = nnh
Offset 9 - Programming Interface
(00h) .......................... RO
Offset A - Sub Class Code
(01h=Audio Device)............... RO
Offset B - Base Class Code
(04h=Multimedia Device) ..... RO
Offset 13-10 - Base Address 0 – SGD Control / Status .. RW
31-16 Reserved
........................................always reads 0
15-8 Base Address
.........................................default = 00h
7-0
00000001b (256 bytes)
Device 0 Offset 2D-2C – Subsystem Vendor ID (0000h)*RO
15-0 Subsystem Vendor ID
..............................default = 0
*This register is RW if function 5-6 Rx44[4] = 1
Device 0 Offset 2F-2E – Subsystem ID (0000h)............. *RO
15-0 Subsystem ID
............................................default = 0
*This register is RW if function 5-6 Rx44[4] = 1
Offset 34 – Capture Pointer (C0h) ................................... RO
Offset 3C - Interrupt Line................................................ RW
7-4
Reserved
........................................always reads 0
3-0
Audio Interrupt Routing
0000 Disabled ................................................. default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 IRQ8
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 IRQ13
1110 IRQ14
1111 Disabled
APIC (See Device 17 Function 0 Rx4D[7])
x000 IRQ16
x001 IRQ17
x010 IRQ18
… …
x111 IRQ23
Offset 3D - Interrupt Pin
(03h) ......................................... RO
Offset 3E - Minimum Grant
(00h).................................... RO
Offset 3F - Maximum Latency
(00h) ................................ RO



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