VT8235 datasheet(102/145 Pages) VIA

102 / 145 page

VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-96-

Device 17 Function 1 Enhanced IDE Controller Registers

UrpuytvrÃDp

XrÃ8rp

Offset 44 - Miscellaneous Control 1 (08h) .......................RW

7-5

Reserved

........................................ always reads 0

PIO Read Pre-Fetch Byte Counter

Determines whether the amount of data prefetched

under PIO read is limited.

Disable (no limit) .................................. default

Enable. The maximum number of bytes that

can be prefetched is determined by Rx61-

60[11:0] for the primary channel and Rx69-

68[11:0] for the secondary channel.

Bus Master IDE Status Register Read Retry

Determines whether a read to the bus master IDE

status register is retried when DMA operation is not

complete.

Disable. Reads will return status even if DMA

operation is not complete.

Enable.

Reads of the status register are

automatically retried while DMA operation is

not complete. .........................................default

Packet Command Prefetching

Determines whether prefetching is enabled for packet

commands.

Packet commands are commands for

ATAPI, which is used for operating devices such as

CD-ROM drives.

Disable .................................................. default

Enable

Reserved

........................................ always reads 0

UltraDMA Host Must Wait for First Transfer

Before Termination

Enable. The UltraDMA host must wait until at

least the first transfer is completed before it

can terminate a transaction. ................... default

Disable

Offset 45 - Miscellaneous Control 2 (20h)....................... RW

Reserved

........................................always reads 0

Interrupt Steering Swap

Controls whether primary and secondary channel

interrupts are swapped.

Primary channel interrupt is steered to IRQ14,

Secondary channel is steered to IRQ15 . default

Primary channel interrupt is steered to IRQ15,

Secondary channel interrupt steered to IRQ14

Reserved

...................................... always reads 1

Rx3C Write Protect

Disable (writes to Rx3C are allowed) .... default

Enable (writes to Rx3C are ignored). Under

Native Mode (Rx9[2]=1 or Rx9[0]=1) Rx3C

should not be write protected as it is used to

route IRQ lines.

“Memory-Read-Multiple” Command

Disable ................................................... default

Enable

“Memory-Write-and-Invalidate” Command

Disable ................................................... default

Enable

1-0

Reserved

........................................always reads 0

Offset 46 - Miscellaneous Control 3 (C0h)...................... RW

Primary Channel Read DMA FIFO Flush

Disable

Enable. The primary channel DMA FIFO is

flushed when an interrupt request is generated

................................................... default

Secondary Channel Read DMA FIFO Flush

Disable

Enable. The secondary channel DMA FIFO is

flushed when an interrupt request is generated

................................................... default

5-0

Reserved

........................................always reads 0

VT8235 Datasheet(PDF) 102 Page - VIA Technologies, Inc.

VT8235 Datasheet(HTML) 102 Page - VIA Technologies, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL