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STAC9752A Datasheet(PDF) 28 Page - Integrated Device Technology |
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STAC9752A Datasheet(HTML) 28 Page - Integrated Device Technology |
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28 / 106 page ![]() STAC9752A/9753A AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK PC AUDIO IDT™ 28 STAC9752A/9753A V 1.5 1206 AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK The following are potential 24.576MHz clock options available to a Secondary CODEC: • Using an external 24.576 MHz signal source (external oscillator or AC‘97 Digital Controller) • Using the Primary’s crystal out • Using the Primary’s BIT_CLK output to derive 24.576MHz See section 2.2.4: page17 for clock frequencies supported and configurations. 4.5. STAC9752A/9753A as a Primary CODEC Primary devices are required to support correctly either of the following clocking options: • 24.576MHz crystal attached to XTAL_IN and XTAL_OUT • 24.576MHz external oscillator provided to XTAL_IN • 12.288MHz oscillator provided to the BIT_CLK input The Primary device may also optionally support the following clocking option: • 14.318MHz external oscillator provided to XTAL_IN See section 2.2.4: page17 for clock frequencies supported and configurations. 4.5.1. STAC9752A/9753A as a Secondary CODEC Secondary devices are required to function correctly using one or more of the following clocking options: • 24.576MHz external oscillator provided to XTAL_IN (synchronous and in phase with Primary 24.576MHz clock) • BIT_CLK input provided by the Primary. In this mode, a clock at XTAL_IN (Pin 2) is ignored. See section 2.2.4: page17 for clock frequencies supported and configurations. 4.6. AC-Link Power Management 4.6.1. Powering down the AC-Link The AC-Link signals can be placed in a low power mode. When AC‘97’s Powerdown Register (26h) is programmed to the appropriate value, both BIT_CLK and SDATA_IN are brought to and held at a logic low voltage level. After signaling a reset to AC‘97, the AC‘97 Controller should not attempt to play or capture audio data until it has sampled a CODEC Ready indication from AC‘97. |
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