STAC9752A datasheet(37/106 Pages) IDT

37 / 106 page

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

IDT™

STAC9752A/9753A

V 1.5 1206

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

Within slot 0 the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the

entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains

at least one time slot of valid data. The next 12 bit positions sampled by AC‘97 indicate which of the

corresponding 12 time slots contain valid data. In this way data streams of differing sample rates can

be transmitted across AC-Link at its fixed 48 KHz audio frame rate.

The two LSBs of Slot 0 transmit the CODEC ID used to distinguish Primary and Secondary CODEC

5.3.2.

Slot 1: Command Address Port

The command port is used to control features, and monitor status (see AC-Link input frame Slots 1

and 2) for AC‘97 CODEC functions including, but not limited to, mixer settings, and power manage-

ment (refer to the control register section of this specification).

The control interface architecture supports up to 64 16-bit read/write registers, addressable on even

byte boundaries. Only the even registers (00h, 02h, etc.) are currently defined, odd register (01h,

03h, etc.) accesses are reserved for future expansion.

Note that shadowing of the control register file on the AC‘97 Controller is an option left open to the

implementation of the AC‘97 Controller. The AC‘97 CODEC’s control register file is nonetheless

required to be readable as well as writeable to provide more robust testability.

AC-Link output frame slot 1 communicates control register address, and write/read command infor-

mation to the STAC9752A/9753A.

The first bit (MSB) sampled by AC‘97 indicates whether the current control transaction is a read or a

write operation. The following 7 bit positions communicate the targeted control register address. The

trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC‘97 Control-

ler.

5.3.3.

Slot 2: Command Data Port

The command data port is used to deliver 16-bit control register write data in the event that the cur-

rent command port operation is a write cycle. (as indicated by Slot 1, bit 19)

•

Bit(19:4) Control Register Write Data (Stuffed with 0s if current operation is a read)

•

Bit(3:0)

Reserved

(Stuffed with 0s)

If the current command port operation is a read then the entire slot time must be stuffed with 0s by

the AC‘97 Controller.

Table 8. Command Address Port Bit Assignments

Bit

Description

Comments

Read/Write command

1 = read, 0 = write

18:12

Control Register Index

sixty-four 16-bit locations, addressed on even byte boundaries

11:0

Reserved

Stuffed with 0s

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