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STAC9752A Datasheet(PDF) 36 Page - Integrated Device Technology |
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STAC9752A Datasheet(HTML) 36 Page - Integrated Device Technology |
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36 / 106 page  STAC9752A/9753A AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK PC AUDIO IDT™ 36 STAC9752A/9753A V 1.5 1206 AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK valid time slot, the AC‘97 Controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s. As an example, consider an 8-bit sample stream that is being played out to one of the STAC9752A/ 9753A DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next 12 bit-positions which are stuffed with 0s by the AC‘97 Controller. This ensures that regardless of the resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least significant bits. When mono audio sample streams are output from the AC‘97 Controller it is necessary that BOTH left and right sample stream time slots be filled with the same data. 5.3.1. Slot 0: TAG / CODEC ID Note: The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11. Table 7. Output Slot 0 Bit Definitions Bit Description 15 Frame Valid 14 Slot 1 Primary CODEC Valid Command Address bit (Primary CODEC only) 13 Slot 2 Primary CODEC Valid Command Data bit (Primary CODEC only) 12-3 Slot 3-12 Valid Data bits 12 Slot 3: PCM Left channel 11 Slot 4: PCM Right channel 10 Slot 5: Modem Line 1 (not used on STAC9752A/9753A) 9 Slot 6: Alternative PCM1 Left 8 Slot 7: Alternative PCM2 Left 7 Slot 8: Alternative PCM2 Right 6 Slot 9: Alternative PCM1 Right 5 Slot 10: SPDIF Left 4 Slot 11: SPDIF Right 3 Slot 12: Audio GPIO 2 Reserved (Set to 0) 1-0 2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary) SYNC B I T_CLK SDATA_OUT slot1 slot2 End of previous audio frame valid Frame SYNC asserted first SDATA_OUT bit of frame SYNC detected by codec |
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