STAC9752A datasheet(34/106 Pages) IDT

34 / 106 page

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

IDT™

STAC9752A/9753A

V 1.5 1206

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

AC-Link input frame signal which active output slots require data from the AC‘97 Digital Controller in

the next audio output frame. An active output slot is defined as any slot supported by the CODEC

that is not in a power-down state. For fixed 48KHz operation the SLOTREQ bits are always set

active (low) and a sample is transferred in each frame.

For variable sample rate input, the tag bit for each input slot indicates whether valid data is present

or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN

(CODEC to Controller), the CODEC sets the TAG bit; for SDATA_OUT (Controller to CODEC), the

CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame.

The VRM (Variable Rate Mic Audio) bit in the Extended Audio Status and Control Register controls

the optional MIC ADC input behavior in the same way that VRA = 1 controls the PCM ADC.

5.2.2.1.

SLOTREQ Behavior and Power Management

SLOTREQ bits for fixed rate, powered down, and all unsupported Slots should be driven with 0s for

maximum compatibility with the original AC '97 Component Specification. When a DAC channel is

powered down, it disappears completely from the serial frame: output tag and slot are ignored, and

the SLOTREQ bit is absent (forced to zero).

When the Controller wants to power-down a channel, all it needs to do is:

Disable source of DAC samples in Controller

Set PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh

When it wants to power up the channel, all it needs to do is:

Clear PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh

Enable source of DAC samples in Controller

5.2.3.

Primary and Secondary CODEC Register Addressing

The 2-bit CODEC ID field in the LSBs of Output Slot 0 is an addition to the original AC-Link protocol

that enables an AC‘97 Digital Controller to independently access Primary and Secondary CODEC

registers.

For Primary CODEC access, the AC‘97 Digital Controller:

Sets the AC-Link Frame valid bit (Slot 0, bit 15).

Validates the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13).

Sets a zero value (00) into the CODEC ID field (Slot 0, bits 1 and 0).

Transmits the desired Primary CODEC Command Address and Command Data in Slots 1 and

For Secondary CODEC access, the AC‘97 Digital Controller:

Sets the AC-Link Frame valid bit (Slot 0, bit 15).

STAC9752A Datasheet(PDF) 34 Page - Integrated Device Technology