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STAC9752A Datasheet(PDF) 70 Page - Integrated Device Technology |
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STAC9752A Datasheet(HTML) 70 Page - Integrated Device Technology |
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70 / 106 page ![]() STAC9752A/9753A AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK PC AUDIO IDT™ 70 STAC9752A/9753A V 1.5 1206 AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK 7.2.5. GPIO Pin Configuration Register (4Ch) Default: 0003h 7.2.6. GPIO Pin Polarity/Type Register (4Eh) Default: FFFFh 7.2.7. GPIO Pin Sticky Register (50h) Default: 0000h D15 D14 D13 D12 D11 D10 D9 D8 Reserved D7 D6 D5 D4 D3 D2 D1 D0 Reserved GC1 (GPIO1) GC0 (GPIO0) Bit(s) Access Reset Value Name Description 15:2 Read Only 0 Reserved Bit not used, should read back 0 1 Read / Write 1 GC1 0 = GPIO1 configured as output 1 = GPIO1 configured as input 0 Read / Write 1 GC0 0 = GPIO0 configured as output 1 = GPIO0 configured as input D15 D14 D13 D12 D11 D10 D9 D8 Reserved D7 D6 D5 D4 D3 D2 D1 D0 Reserved GP1 (GPIO1) GP0 (GPIO0) Bit(s) Access Reset Value Name Description 15:2 Read Only 0 Reserved Bit not used, should read back 0 1 Read / Write 1 GP1 0 = GPIO1 Input Polarity Inverted, CMOS output drive. 1 = GPIO1 Input Polarity Non-inverted, Open-Drain output drive. 0 Read / Write 1 GP0 0 = GPIO0 Input Polarity Inverted, CMOS output drive. 1 = GPIO0 Input Polarity Non-inverted, Open-Drain output drive. D15 D14 D13 D12 D11 D10 D9 D8 Reserved D7 D6 D5 D4 D3 D2 D1 D0 Reserved GS1 (GPIO1) GS0 (GPIO0) Bit(s) Access Reset Value Name Description 15:2 Read Only 0 Reserved Bit not used, should read back 0 |
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