STAC9752A datasheet(33/106 Pages) IDT

33 / 106 page

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

IDT™

STAC9752A/9753A

V 1.5 1206

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

5.2.1.

AC-Link Variable Sample Rate Operation

The AC-Link serial interconnect defines a digital data and control pipe between the Controller and

the CODEC. The AC-Link supports twelve 20-bit slots at 48KHz on SDATA_IN and SDATA_OUT.

The time division multiplexed (TDM) “slot-based” architecture supports a per-slot valid tag infrastruc-

ture that the source of each slot’s data sets or clears to indicate the validity of the slot data within the

current audio frame. This tag infrastructure can be used to support transfers between Controller and

CODEC at any sample rate.

5.2.2.

Variable Sample Rate Signaling Protocol

AC-Link’s tag infrastructure imposes FIFO requirements on both sides of the AC-Link. For example,

in passing a 44.1KHz stream across the AC-Link, for every 480 audio output frames that are sent

across, 441 of them must contain valid sample data. Does the AC‘97 Digital Controller pass all 441

PCM samples followed by 39 invalid slots? Or does the AC‘97 Digital Controller evenly interleave

valid and non-valid slots? Each possible method brings with it different FIFO requirements. To

achieve interoperability between AC‘97 Digital Controllers and CODECs designed by different man-

ufacturers, it is necessary to standardize the scheme for at least one side of the AC-Link so that the

FIFO requirements will be common to all designs. The CODEC side of the AC-Link is the focus of

this standardization.

The new standard approach calls for the addition of “on demand” slot request flags. These flags are

passed from the CODEC to the AC‘97 Digital Controller during every audio input frame. Each time

the AC‘97 Digital Controller sees one or more of the newly-defined slot request flags set active (low)

in a given audio input frame, it knows that it must pass along the next PCM sample for the corre-

sponding slot(s) in the AC-Link output frame that immediately follows.

The VRA (Variable Rate Audio) bit in the Extended Audio Status and Control Register must be set to

1 to enable variable sample rate audio operation. Setting the VRA = 1 has two functions:

Enables PCM DAC/ADC conversions at variable sample rates by write enabling Sample Rate

Registers 2C-34h.

Enables the on demand CODEC-to-Controller signaling protocol using SLOTREQ bits that

becomes necessary when a DAC’s sample rate varies from the 48KHz AC-Link serial frame

rate.

The table below summarizes the behavior:

Note: If more than one CODEC is being used with the SAME controller DMA engine, VRA should NOT be

used.

For variable sample rate output, the CODEC examines its sample rate control registers, the state of

its FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each AC-Link output frame to

determine which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current

Table 6. VRA Behavior

AC‘97 Functionality

VRA = 0

VRA = 1

SLOTREQ bits

always 0 (data each frame)

0 or 1 (data on demand)

sample rate registers

forced to 48KHz

writable

STAC9752A Datasheet(PDF) 33 Page - Integrated Device Technology

STAC9752A Datasheet(HTML) 33 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL