STAC9752A datasheet(76/106 Pages) IDT

76 / 106 page

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

IDT™

STAC9752A/9753A

V 1.5 1206

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

Default: 00xxh, see table 23: page77.

D15

D14

D13

D12

D11

D10

INV

DL4

DL3

DL2

DL1

DL0

Reserved

FIP

Bit(s) Reset Value

Name

Description

Gain Sign Bit: The CODEC updates this bit with the sign of the gain value

present in G[3:0]. The BIOS updates this to take into consideration external

amplifiers or other external logic when relevant.

G[4] indicates whether the value is a gain or attenuation.

Gain in the G4 bit is in terms of dB.

This bit is Read/Write and only reset on POR and not by RESET#.

14-11

G3:G0

Gain Bits: The CODEC updates these bits with the gain value (dB relative to

level-out) in 1.5dBV increments. The BIOS updates these to take into

consideration external amplifiers or other external logic when relevant.

G[0:3] indicates the magnitude of the gain. G[4] indicates whether the value is a

gain or attenuation.

For Gain/Attenuation settings, see Table 24: page77.

These bits are read/write and are not reset on RESET#.

INV

Inversion bit: Indicates that the CODEC presents a 180 degree phase shift to the

signal.

0h - No inversion reported

1h - Inverted

This bit is read/write and is not reset on RESET#.

BIOS should invert for each inverting gain stage.

9-5

DL4:DL0

Buffer delays: CODEC will provide number a delay measurement for the input

and output channels. Software will use this value to accurately calculate audio

stream position with respect to what is been reproduced or recorded. These

values are in 20.83

µsec (1/48000 second) units.

For output channels, this timing is from the end of AC Link frame in which the

sample is provided, until the time the analog signal appears at the output pin. For

input streams, this is from when the analog signal is presented at the pin until the

representative sample is provided on the AC Link.

Analog in and out paths are not considered as part of this delay.

The measurement is a 'typical' measurement, at a 48KHz sample rate, with

minimal in-CODEC processing (i.e., 3D effects are turned off.)

00h - Information not provided

01h…1Eh - Buffer delay in 20.83

µsec units

1Fh - reserved

These bits are read/write and are not reset on RESET#.

The default value is the delay internal to the CODEC. The BIOS may add to this

value the known delays external to the CODEC, such as for an external

amplifier.

STAC9752A Datasheet(PDF) 76 Page - Integrated Device Technology

STAC9752A Datasheet(HTML) 76 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL