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STAC9752A Datasheet(PDF) 64 Page - Integrated Device Technology |
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STAC9752A Datasheet(HTML) 64 Page - Integrated Device Technology |
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64 / 106 page  STAC9752A/9753A AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK PC AUDIO IDT™ 64 STAC9752A/9753A V 1.5 1206 AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK one of three secondary CODECs. The AMAP bit, D9, will return a 1 indicating that the CODEC sup- ports the optional “AC’97 2.3 Compliant AC-Link Slot to Audio DAC Mappings”. The default condition assumes that 00 is loaded in the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With 00 in the DSA1 and DSA0 bits, the CODEC slot assignments are as per the AC’97 specification recom- mendations. If the DSA1 and DSA0 bits do not contain 00, the slot assignments are as per the table in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1 indicat- ing that the CODEC supports the optional variable sample rate conversion as defined by the AC’97 specification. Note: 1) External CID pin status (from analog), these bits are the logical inversion of the pin polarity (pin 45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock source (in primary mode only). Secondary mode can either be through BIT CLK driven or 24MHz clock driver, with XTAL_OUT floating. Note: 2) If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not available. To disable SPDIF, use an 1K Ω - 10KΩ external pullup resistor. 7.1.20. Extended Audio Control/Status (2Ah) Default: 0400h* (*default depends on CODEC ID) Table 19. Extended Audio ID Register Functions Bit Name Access Reset Value Function 15:14 ID [1,0] Read only variable 00 = XTAL_OUT grounded (Note Note:) CID1#,CID0# = XTAL_OUT crystal or floating 13:12 Reserved Read only 00 Bits not used, should read back 00 11:10 REV[1:0] Read only 10 Indicates CODEC is AC’97 Rev 2.3 compliant 9:6 RSVD Read only 0 Reserved 5:4 DSA [1,0] Read/Write 00 DAC slot assignment If CID[1:0] = 00 then DSA[1:0] resets to 00 If CID[1:0] = 01 then DSA[1:0] resets to 01 If CID[1:0] = 10 then DSA[1:0] resets to 01 If CID[1:0] = 11 then DSA[1:0] resets to 10 00 = left slot 3, right slot 4 01 = left slot 7, right slot 8 10 = left slot 6, right slot 9 11 = left slot 10, right slot 11 3 RSVD Read only 0 Reserved 2 SPDIF Read only 1 0 = SPDIF pulled high on reset, SPDIF disabled 1 = default, SPDIF enabled (Note Note:) 1 RSVD Read only 0 Reserved 0 VRA Read only 1 Variable sample rates supported (Always = 1) D15 D14 D13 D12 D11 D10 D9 D8 VCFG Reserved SPCV Reserved D7 D6 D5 D4 D3 D2 D1 D0 Reserved SPSA1 SPSA0 RSRVD SPDIF RSRVD VRA enable |
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