STAC9752A datasheet(38/106 Pages) IDT

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STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

IDT™

STAC9752A/9753A

V 1.5 1206

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

5.3.4.

Slot 3: PCM Playback Left Channel

AC-Link output frame slot 3 is the composite digital audio left playback stream. In a typical “Games

Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the

AC‘97 Controller or host processor) with music synthesis output samples. If a sample stream of res-

olution less than 20-bits is transferred, the AC‘97 Controller must stuff all trailing non-valid bit posi-

tions within this time slot with 0s.

The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.3.5.

Slot 4: PCM Playback Right Channel

AC-Link output frame slot 4 is the composite digital audio right playback stream. In a typical “Games

Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the

AC‘97 Controller or host processor) with music synthesis output samples. If a sample stream of res-

olution less than 20-bits is transferred, the AC‘97 Controller must stuff all trailing non-valid bit posi-

tions within this time slot with 0s.

The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.3.6.

Slot 5: NOT USED (Modem Line 1 Output Channel)

Audio output frame slot 5 is reserved for modem operation and is not used by the STAC9752A/

9753A .

5.3.7.

Slot 6 -11: DAC

The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.

5.3.8.

Slot 12: Audio GPIO Control Channel

AC-Link output frame slot 12 contains the audio GPIO control outputs.

5.4.

AC-Link Input Frame (SDATA_IN)

The AC-Link input frame data streams correspond to the multiplexed bundles of all digital input data

targeting the AC‘97 Controller. As is the case for an audio output frame, each AC-Link input frame

consists of twelve 20-bit time slots. Slot 0 is a special reserved time slot containing 16-bits which are

used for AC-Link protocol infrastructure.

The following diagram illustrates the time slot-based AC-Link protocol.

Figure 17. STAC9752A/9753A Audio Input Frame

A new AC-Link input frame begins with a low to high transition of SYNC. SYNC is synchronous to

the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97

CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of

STAC9752A Datasheet(PDF) 38 Page - Integrated Device Technology

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