STAC9752A datasheet(89/106 Pages) IDT

89 / 106 page

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

IDT™

STAC9752A/9753A

V 1.5 1206

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

10. TESTABILITY

The STAC9752A/9753A has two test modes. One is for ATE in-circuit test and the other is restricted

for IDT’s internal use. STAC9752A/9753A enters the ATE in-circuit test mode if SDATA_OUT is

sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs

(BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of

the AC'97 controller. Use of the ATE test mode is the recommended means of removing the CODEC

from the AC-Link when another CODEC is to be used as the primary. This case will never occur dur-

ing standard operating conditions. Once either of the two test modes have been entered, the

STAC9752A/9753A must be issued another RESET# with all AC-Link signals held low to return to

the normal operating mode.

10.1. ATE Test Mode

ATE test mode allows for in-circuit testing to be completed at board level. For this to work, the out-

puts of the device must be driven to a high impedance state (Z). Internal pullups for digital I/O pins

must be disabled in this mode. This mode initiates on the rising edge of RESET# pin. Only a cold

reset will exit the ATE Test Mode.

Table 32. ATE Test Mode Operation

Note: Pins 31, 33, and 34 are NO CONNECTS.

Table 31. Test Mode Activation

SYNC

SDATA_OUT

Description

Normal AC '97 operation

ATE Test Mode

IDT Internal Test Mode

Reserved

Pin Name

Pin #

Function

Description

SDATA_OUT

Must be held high at the rising edge of RESET#

BIT_CLK

SDATA_IN

SYNC

Must be held low at rising edge of RESET#

RESET#

N.C.

Always an input

N.C.

Always an input

N.C.

Always an input

GPIO0

GPIO1

CID0

CID1

EAPD

SPDIF

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