STAC9752A datasheet(35/106 Pages) IDT

35 / 106 page

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

IDT™

STAC9752A/9753A

V 1.5 1206

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

Places a non-zero value (01, 10, or 11) into the CODEC ID field (Slot 0, bits 1 and 0).

Transmits the desired Secondary CODEC Command Address and Command Data in Slots 1

and 2.

Secondary CODECs disregard the Command Address and Command Data (Slot 0, bits 14 and 13)

tag bits. In a sense the Secondary CODEC ID field functions as an alternative Valid Command

Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator.

Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state

of the Secondary CODEC ID bits) if it is not valid. AC‘97 Digital Controllers should set the frame valid

bit for a frame with a Secondary register access, even if no other bits in the output tag slot except the

Secondary CODEC ID bits are set.

5.3.

AC-Link Output Frame (SDATA_OUT)

The AC-Link output frame data streams correspond to the multiplexed bundles of all digital output

data targeting AC‘97’s DAC inputs, and control registers. As mentioned earlier, each AC-Link output

frame supports up to twelve 20-bit outgoing data time slots. Slot 0 is a special reserved time slot

containing 16-bits which are used for AC-Link protocol infrastructure.

Figure 15 illustrates the time slot based AC-Link protocol.

Figure 15. AC-Link Audio Output Frame

A new AC-Link output frame begins with a low to high transition of SYNC. SYNC is synchronous to

the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97

CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of

AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 Con-

troller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit posi-

tion is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97

CODEC on the following falling edge of BIT_CLK. This sequence ensures that data transitions and

subsequent sample points for both incoming and outgoing data streams are time aligned.

Figure 16. Start of an Audio Output Frame

SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions

stuffed with 0s by the AC‘97 Controller. If there are less than 20 valid bits within an assigned and

SYNC

BIT_CLK

SDATA_OUT

slot1

slot2

End of previous audio frame

slot(12)

"0"

Data Phase

20.8 uS (48 kHZ)

Tag Phase

12.288 MHz

Time Slot "Valid" Bits

Slot 1

Slot 2

Slot 3

Slot 12

("1" = time slot contains valid PCM data)

CID1

CID0

valid

"0"

Frame

"0"

STAC9752A Datasheet(PDF) 35 Page - Integrated Device Technology

STAC9752A Datasheet(HTML) 35 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL