STAC9752A datasheet(66/106 Pages) IDT

66 / 106 page

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

IDT™

STAC9752A/9753A

V 1.5 1206

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot

in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable

“on-demand” data transfers. If the VRA enable bit is not set, the CODEC will default to 48 KHz trans-

fers and every audio frame will include an active slot request flag and data is transferred every

frame.

For variable sample rate output, the CODEC examines its sample rate control registers, the state of

the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to

determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current

audio input frame for active output slots, which will require data in the next audio output frame.

For variable sample rate input, the tag bit for each input slot indicates whether valid data is present

or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN

(CODEC to controller), the CODEC sets the TAG bit; for SDATA_OUT (controller to CODEC), the

CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. Whenever VRA is

set to 0, the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz).

7.1.20.2.

SPDIF

The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the

SPDIF functionality within the STAC9752A/9753A. If the SPDIF is set to a 1, then the function is

enabled. When set to a 0, it is disabled.

7.1.20.3.

SPCV (SPDIF Configuration Valid)

The SPCV bit is read only and indicates whether or not the SPDIF system is set up correctly. When

SPCV is a 0, it indicates the system configuration is invalid. When SPCV is a 1, it indicates the sys-

tem configuration is valid.

7.1.20.4.

SPSA1, SPSA0 (SPDIF Slot Assignment)

SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following

details the slot assignment relationship between SPSA1 and SPSA0.

The STAC9752A/9753A are AMAP compliant with the following table.

Table 20. AMAP compliant

CODEC

Function

SPSA=00

Slot Assignment

SPSA=01

Slot Assignment

SPSA=10

Slot Assignment

SPSA=11

Slot Assignment

2-ch Primary with

SPDIF

3 & 4

7 & 8

6 & 9

10 & 11

2-ch Dock CODEC

with SPDIF

3 & 4

7 & 8

6 & 9

10 & 11

+2-ch Surr w/ SPDIF

3 & 4

7 & 8

6 & 9

10 & 11

+2-ch Cntr/LFE with

SPDIF

3 & 4

7 & 8

6 & 9

10 & 11

Note:* is the default slot assignment

STAC9752A Datasheet(PDF) 66 Page - Integrated Device Technology

STAC9752A Datasheet(HTML) 66 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL