STAC9752A datasheet(29/106 Pages) IDT

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STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

IDT™

STAC9752A/9753A

V 1.5 1206

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

Figure 13. STAC9752A/9753A Powerdown Timing

BIT_CLK and SDATA_IN are transitioned low immediately following decode of the write to the Pow-

erdown Register (26h) with PR4. When the AC‘97 Controller driver is at the point where it is ready to

program the AC-Link into its low power mode, slots 1 and 2 are assumed to be the only valid stream

in the audio output frame.

After programming the AC‘97 device to this low power, halted mode, the AC‘97 Controller is required

to drive and keep SYNC and SDATA_OUT low.

Once the AC‘97 CODEC has been instructed to halt BIT_CLK, a special “wake-up” protocol must be

used to bring the AC-Link to the active mode since normal audio output and input frames can not be

communicated in the absence of BIT_CLK.

4.6.2.

Waking up the AC-Link

There are two methods for bringing the AC-Link out of a low power, halted mode. Regardless of the

method, it is the AC‘97 Controller that performs the wake-up task.

4.6.2.1.

Controller Initiates Wake-up

AC-Link protocol provides for a “Cold AC‘97 Reset”, and a “Warm AC‘97 Reset”. The current power-

down state would ultimately dictate which form of AC‘97 reset is appropriate. Unless a “cold” or “reg-

ister” reset (a write to the Reset Register) is performed, wherein the AC‘97 registers are initialized to

their default values, registers are required to keep state during all powerdown modes.

Once powered down, re-activation of the AC-Link via re-assertion of the SYNC signal must not occur

for a minimum of four audio frame times following the frame in which the powerdown was triggered.

When AC-Link powers up the CODEC indicates readiness via the CODEC Ready bit (input slot 0, bit

15).

4.6.2.2.

CODEC Initiates Wake-up

The STAC9752A/9753A (running off Vaux) can trigger a wake event (PME#) by transitioning

SDATA_IN from low to high and holding it high until either a warm or cold reset is observed on the

SYNC

BIT_CLK

SDATA_OUT

Note: BIT_CLK not to scale

SDATA_IN

TAG

Write to

0x20

slot 2

per

frame

DATA

PR4

TAG

slot 2

per

frame

STAC9752A Datasheet(PDF) 29 Page - Integrated Device Technology

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