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PM7346 Datasheet(PDF) 213 Page - PMC-Sierra, Inc |
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PM7346 Datasheet(HTML) 213 Page - PMC-Sierra, Inc |
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213 / 419 page  PM7346 S/UNI-QJET DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3 PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 192 Register 049H, 149H, 249H, 349H: J2-FRMR Error/Xbit Interrupt Status Bit Type Function Default Bit 7 R CRCEI X Bit 6 R FRMEI X Bit 5 R BPVI X Bit 4 R EXZI X Bit 3 R XBITI X Bit 2 R X3 X Bit 1 R X2 X Bit 0 R X1 X CRCEI The CRCEI bit is set to logic 1 if a failed CRC-5 check occurs. CRCEI is cleared when this register is read. FRMEI The FRMEI bit is set to logic 1 if an errored framing bit occurs. FRMEI is cleared when this register is read. BPVI The BPVI bit is set to logic 1 if a bipolar violation that is not part of a valid B8ZS code occurs (when UNI is logic 0 in the J2-FRMR Configuration Register) or if a 0 to 1 transition is detected on RLCV (when UNI is logic 1). BPVI is cleared when this register is read. EXZI The EXZI bit is set to logic 1 upon reception of eight-or-more consecutive zeroes. EXZI remains logic 0 while UNI is set to logic 1 in the J2_FRMR Configuration Register. EXZI is cleared when this register is read. XBITI The XBITI bit is set to logic 1 if a change in the debounced (if XBIT_DEB is set to logic 1) x-bits (X1, X2, and X3) is detected. XBITI is cleared when this register is read. |
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