PM7346 datasheet(216/419 Pages) PMC

216 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 195

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

R/W

PLDAIS

Bit 4

R/W

PHYAIS

Bit 3

R/W

DCRC

Bit 2

R/W

DLOS

Bit 1

R/W

DBPV

Bit 0

R/W

DFERR

DFERR:

The DFERR bit controls the insertion of framing alignment signal errors.

When DFERR is set to logic 1, the framing alignment signal is inverted.

When DFERR is set to logic 0, the framing alignment signal is not inverted.

DBPV:

The DBPV bit controls the insertion of single bipolar violations. When DBPV

bit transitions from 0 to 1, a violation is generated by masking the first

violation pulse of a B8ZS signature. To generate another violation, this bit

must first be written to 0 and then to logic 1 again. When DBPV is a logic 0,

no violation is generated.

DLOS:

When set to logic 1, the DLOS bit forces the unipolar and bipolar outputs of

the J2 TRAN to be all zeros. When DLOS is logic 0, the outputs of the J2

TRAN operate normally.

DCRC:

When set to logic 1, a the CRC-5 check bits (e1-5) are inverted before

transmission. DCRC inverts the e1-5 bits even if CDIS of the J2 TRAN

Configuration register is set to logic 1.

PM7346 Datasheet(PDF) 216 Page - PMC-Sierra, Inc

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