PM7346 datasheet(220/419 Pages) PMC

220 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 199

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

R/W

Reserved

Bit 3

R/W

MEN

Bit 2

R/W

Bit 1

R/W

Bit 0

R/W

EN:

The EN bit controls the overall operation of the RDLC. When EN is set to

logic 1, RDLC is enabled; when set to logic 0, RDLC is disabled. When RDLC

is disabled, the RDLC FIFO buffer and interrupts are all cleared. When RDLC

is enabled, it will immediately begin looking for flags.

TR:

Setting the terminate reception (TR) bit to logic 1 forces the RDLC to

immediately terminate the reception of the current data frame, empty the

RDLC FIFO buffer, clear the interrupts, and begin searching for a new flag

sequence. The RDLC handles a terminate reception event in the same

manner as it would the toggling of the EN bit from logic 1 to logic 0 and back

to logic 1. Thus, the RDLC state machine will begin searching for flags. An

interrupt will be generated when the first flag is detected. The TR bit will reset

itself to logic 0 after the register write operation is completed and a rising and

falling edge occurs on the internal datalink clock input. If the RDLC

Configuration Register is read after this time, the TR bit value returned will be

logic 0.

MEN:

Setting the Match Enable (MEN) bit to logic 1 enables the detection and

storage in the RDLC FIFO of only those packets whose first data byte

matches either of the bytes written to the Primary or Secondary Match

Address Registers, or the universal all ones address. When the MEN bit is

logic 0, all packets received are written into the RDLC FIFO.

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