TMPR3916 datasheet(195/225 Pages) TOSHIBA

195 / 225 page

Chapter 10 Asynchronous Serial Interface (UART)

Preliminary

10-20

Receive operation:

(7, 8-bit length multi controller system; RWUB=1 for data skip)

789

bit0

bit7

789

SIOCLK

SIN

Valid bit0

Valid bit7

10 11

789

10 11

Wake Up bit = 0

SPINTREQ*

789

10 11

Stop bit

data

SPINTREQ*

If Framing Error

Occur

Over Run Error

DMA/Interrupt Status Reg. <ERI >=1

Figure 10.3.4 Receiving 7 or 8 Bit Data Skip Multi Controller Environment

Transmit operation

bit0

bit7

SIOCLK

SOUT

TRANS. FIFO to

Trans. Shift Reg.

Shift-Out

Timing

Start Bit

(Wake Up Bit)

Stop Bit

bit n

Parity Bit

Figure 10.3.5 Transmitting 8 Bit Data

Transmit halt timing by CTS*

bit0

SIOCLK

SOUT

TRANS. FIFO to

Trans. Shift Reg.

Shift-Out

Timing

Start Bit

bit n

CTS*

Stop Bit

Trans. halt

Trans,start

Figure 10.3.6 Transmitting HALT Command

When CTS becomes 1 during data transmission, the data transfer halts after completing the current

data transmission. Despite the halt, the next data is stored in the transmitter shift register. The

transmission is restarted at the first shift out pulse after CTS becomes low.

TMPR3916 Datasheet(PDF) 195 Page - Toshiba Semiconductor

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