TMPR3916 datasheet(193/225 Pages) TOSHIBA

193 / 225 page

Chapter 10 Asynchronous Serial Interface (UART)

Preliminary

10-18

10.2.8

Baud rate control register (SIBGR)

Bit

Name



Bit

987

Name



BCLK

BRD

Bit

Name

Function

Reset

Value

R/W

31:11



Wired to zero

10:8

BCLK

Baud Rate Generator Clock

Specifies the prescaler for the input clock of baud rate generator.

000 = 1/2 system frequency

001 = 1/8 system frequency

010 = 1/32 system frequency

011 = 1/128 system frequency

1xx = system frequency (prescaler bypass)

011

R/W

7:0

BRD

Baud Rate Divisor

Set the baud rate divisor.

0xFF

R/W

10.2.9

Transmitter FIFO register (SITFIFO)

Bit

Name



TXD

Bit

Name

Function

Reset

Value

R/W

31:8



Wired to zero

7:0

TXD

Transmit data

Data written to this register are carried to transmit FIFO.

Note: The bits are write-only.

10.2.10 Receiver FIFO register (SIRFIFO)

Bit

Name



RXD

Bit

Name

Function

Reset

Value

R/W

31:8



Wired to zero

7:0

RXD

Receive Data

Read this register to get next data item from the receiver FIFO.

The Receiver FIFO Register can only be read by a 32-bit-word access.

TMPR3916 Datasheet(PDF) 193 Page - Toshiba Semiconductor

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