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TMPR3916 Datasheet(PDF) 189 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 189 Page - Toshiba Semiconductor

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Chapter 10 Asynchronous Serial Interface (UART)
Preliminary
10-14
10.2.4
DMA/Interrupt Status Register
Bit
31
16
Name
Bit
1514
131211
10
9
8
Name
UBRK
UVALID
UFER
UPER
UOER
ERI
TOUT
TDIS
Bit
7
6
543
210
Name
RDIS
STIS
RFDN
Bit
Name
Function
Reset
Value
R/W
31:16
Wired to zero
0R
15
UBRK
Break
This bit will be set to 1, when break is detected
0
R
14
UVALID
No Data Available
This bit will be set to 1, when the receiver FIFO contains no data.
1
R
13
UFER
Frame Error
This bit will be set to 1, when an error occurred during transfer of the
current frame.
0
R
12
UPER
Parity Error
This bit will be set to 1, when a parity error has been detected.
0
R
11
UOER
Over Run Error
This bit will be set to 1, when an overrun error has occurred.
0
R
10
ERI
Error Interrupt
This bit will be set to 1, when a frame error, parity error or overrun
error has occurred.
Writing 0 to this bit clears it. Writing 1 does not change contents of
this bit.
0
R/W
9
TOUT
Receive Time Out
This bit will be set to 1 immediately after a receive time out occurs.
Writing 0 to this bit clears it. Writing 1 does not change contents of
this bit.
0
R/W
8
TDIS
Transmit DMA/Interrupt Status
This bit will be set to 1, when there is free space in the transmit FIFO.
1
R/W
7
RDIS
Receive DMA/Interrupt Status
This bit will be set to 1, when there are valid data in the receive FIFO.
0
R/W
6
STIS
Status Interrupt Status
This bit will be set to 1, when the status, selected in STIR of Interrupt
Control Register (SIDICE), has changed.
0
R/W
5
Wired to zero
0R
4:0
RFDN
Receive FIFO Data Number Status
Indicating the number of received data frames stored in the receiver
FIFO (0 to 2 entries).
00000
R/W
UBRK, UPER and UOER show the status of the upper FIFO entry. After reading the next data entry,
the UART will update the status information in UBRK, UPER and UOER. That is the reason, why the
software must read status information before reading the data.



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