| Electronic Components Datasheet Search |
|
TMPR3916 Datasheet(PDF) 190 Page - Toshiba Semiconductor |
|
|
|||||||||||||||||||||||||||||
TMPR3916 Datasheet(HTML) 190 Page - Toshiba Semiconductor |
|
190 / 225 page ![]() Chapter 10 Asynchronous Serial Interface (UART) Preliminary 10-15 10.2.5 Status Change Register (SISCISR) Bit 31 8 Name Bit 7 6 543 210 Name OERS CTSS RBRKD TRDY TXALS UBRKD Bit Name Function Reset Value R/W 31:6 Wired to zero 0R 5 OERS Overrun Error This bit will be set to 1, when an overrun error occurs. Cleared by writing 0 0 R/W 4 CTSS CTS terminal Indicates the CTS terminal status. 0 = CTS is deasserted 1 = CTS is asserted 0 R 3 RBRKD Receive Break This bit will be set to 1, when the UART is in break status. 0 R 2 TRDY Tx Ready Set to 1 when the transmitter FIFO has free space at least for one entry of data. 1 R 1 TXALS Tx All Set to 1 when transmitter FIFO and transmitter shift register are empty. 1 R 0 UBRKD UART Break Detect Set to 1 immediately when a break is detected. Cleared by writing 0. 0 R/W UBRKD will be set to 1 as soon as a Break is detected, it will remain 1 until it is explicitly cleared by the software. RBRKD, instead, will be 1 only for the duration of the Break. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |