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TMPR3916 Datasheet(PDF) 187 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 187 Page - Toshiba Semiconductor

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Chapter 10 Asynchronous Serial Interface (UART)
Preliminary
10-12
Bit
Name
Function
Reset
Value
R/W
1:0
UMODE
UART Mode
For the SIO Mode setting.
00 = 8-bit data length
01 = 7-bit data length
10 = Multi controller 8-bit data length
11 = Multi controller 7-bit data length
00
R/W
The reception of a 1-bit stop while in a 2-bit stop length setting does not generate a frame error.
When an external clock is connected to the Serial Clock In pin of the TMPR3916, bit 6 of the SILCR
must be set to 1 to avoid conflicts. It is not possible to connect an external clock and decide to use the
system clock for UART operation.
The OUTSEL bit will have effect only on the frequency of the Serial Clock Out. The Baud rate of the
UART will not depend on the settings of the OUTSEL bit.
The Wake Up Bit for Receive has to be set to 1 if the receiver has to be enabled for receiving an
address frame prior to the data frames. The Wake Up Bit for Transmit has to be set to 1 if an address
frame is being sent prior to sending data frames (an address frame may be followed by several data
frames to the same receiver). Obviously these two bits make sense only in multi controller mode. In a
point-to-point transmission there’s no need to address the receiver.
10.2.3
DMA/Interrupt Control Register (SIDICR)
Bit
31
16
Name
Bit
1514
131211
10
9
8
Name
TDR
RDR
TIR
RIR
SPIR
CTSAC
Bit
7
6
543
210
Name
SIOE
SICTS
SIBRK
SITR
SIAS
SIUB
Bit
Name
Function
Reset
Value
R/W
31:16
Wired to zero
0R
15
TDR
Transmit DMA Request
0 = No DMA request when free space in transmit FIFO
1 = DMA request when free space in transmit FIFO
0
R/W
14
RDR
Receive DMA Request
0 = No DMA request when data in receive FIFO
1 = DMA request when data in receive FIFO
0
R/W
13
TIR
Transmit Interrupt Request
0 = No interrupt when free space in transmit FIFO
1 = Send SIOTX interrupt when free space in transmit FIFO
0
R/W
12
RIR
Receive Interrupt Request
0 = No interrupt when error or time out occurs
1 = When error or time-out occurs send
• SIORX interrupt, when RDR=0,
• SIOEXC interrupt, when RDR=1
0
R/W



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