TMPR3916 datasheet(183/225 Pages) TOSHIBA

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Chapter 10 Asynchronous Serial Interface (UART)

Preliminary

10-8

10.1.10 Error Flags

The following error flags can be risen:

Overrun error

Occurs when there is an overflow of the transmit or of the receive buffer.

Parity error

Occurs when the received parity bit and the calculated parity information are not the same.

Frame error

Occurs when 0 is detected at the stop bit position during receive.

10.1.11 Breaks

A break is detected by the receiver when all bits in a frame are 0 and the stop bit is also 0. When a

break is detected the received data will not be stored and the UART will assert an interrupt to signal the

break condition.

To transmit a break, the TBRK bit of the flow control register must be set to 1. To resume normal

operation the TBRK bit must be set to 0 again.

10.1.12 Receiver Time Out

A receiver time out occurs when the receiver FIFO has at least 1 entry stored and an equivalent of a

2-byte receive time is elapsed from the previous reception. That sets the receiver Time Out bit (TOUT)

in the DMA/Interrupt Status register(SIDISR). Please note that if all data has been fetched from the

FIFO, the Time Out will not be set!

It is recommended not to use the TOUT bit for flow control of the receiver.

10.1.13 Handling of received data and receiver FIFO status bits

The following status information is stored in the receiver FIFO along with the received data:

•

UART receiver break (UBRK)

•

UART available status (UVALID)

•

UART frame error (UFER)

•

UART parity error (UPER)

•

UART overrun error (UOER)

The software can read the status in the DMA/interrupt status register (SIDISR). The status of this

the second one contains a parity error, this will be signaled in the SIDISR only after the first entry has

been read.

Data that has been received without errors can be read from the receiver FIFO. A Receive Interrupt

Request will indicate the presence of new entries in receiver FIFO, if this is enabled. Errors during

reception will be indicated by an exception interrupt request.

Only data that has been received without errors is transferable via DMA. When an error (UFER,

UPER, UOER) or a receive time-out (TOUT) occurs, the receive error is notified and the received data

transfer request is not asserted.

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