TMPR3916 datasheet(179/225 Pages) TOSHIBA

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Chapter 10 Asynchronous Serial Interface (UART)

Preliminary

10-4

10.1.3

Serial Clock Generator

The data rate of serial transmissions depends on the Serial Clock. To generate the Serial Clock it is

possible to use either an external clock or the system clock of the device. Please note that once an

external clock is connected to the device’s I/O pin the user must use this clock, otherwise a conflict will

occur.

Once that the clock source is fixed, this is used to generate the Serial Clock by means of a prescaler

(optional) and a Baud Rate Divisor.

Figure 10.1.4 shows a block diagram of the Serial Clock Generator:

Prescale

Select

Divider

Baud Rate

Divider Value

Selector

external

clock

Clock Select 2

Baud Rate Generator

Prescaler

system

clock

Selector

Clock Select 1

SIOCLK

1/16

OUTSEL

Figure 10.1.4 Serial Clock Generator Structure

The Clock Select 1 and 2 control lines are bits 6 and 5 respectively of the Line Control Register and

allow the user to choose between an internal or external clock, and if the Baud Rate Generator has to be

bypassed. The output clock – if the BRG is bypassed – can be of the same frequency as the input clock

or divided by 16, depending on the value of OUTSEL (Line Control Register).

The SIOCLK is not used as system clock for FIFOs etc, but to synchronize operations. The SIOCLK

is output as Serial Clock Out. The OUTSEL bit will affect the frequency of the Serial Clock Out but not

the baud rate of the UART.

The baud rate generator creates the transmit/receive clock, which regulates the transfer rate for the

serial interface. The baud rate can be calculated by the following formula:

generator

rate

baud

(divisor

prescaler

frequency

input

rate

baud

The input clock (either system or external clock) may be prescaled by the values shown in the SIBGR

registers and then divided according to the BRD field of the same register. Pay attention to the fact that

the clock is actually divided by a value of (BRD+1). The BRD is an 8-bit register, so the divider ranges

from 1 to 256.

Table 10.1.1 shows the output frequency of the baud rate generator (SIOCLK), depending on the

baud rate divisor and the prescaler:

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