TMPR3916 datasheet(180/225 Pages) TOSHIBA

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Chapter 10 Asynchronous Serial Interface (UART)

Preliminary

10-5

Desired Baud

Rate

Baud Rate

Input

Prescaler

Baud Rate

Divisor

Actual Baud

Rate

9600

60 MHz

½ (000)

194 (0xC2)

9615

57600

60 MHz

½ (000)

32 (0x20)

56818

115200

60 MHz

½ (000)

15 (0x0F)

117187

Table 10.1.1 Baud Rate Register Settings for Common Baud Rates

Other Baud Rates may be easily calculated. When choosing the value of the Prescaler and the Baud

Rate Divisor we recommend that the actual baud rate should not differ more than 4.0% from the

nominal value. This is because a certain drift is allowed but if the 4.0% figure is exceeded then the

correct transmission of a frame is not guaranteed anymore.

10.1.4

Transmitter Control

Once that the parameters have been set, writing data into the Transmit FIFO is sufficient for

transmission. During transmission also the parity bit will be calculated and added to the data stream if

the option has been enabled. The data transmission rate will be the one set in the Baud Rate Register.

Make sure that both receiver and transmitter have the same settings for Baud Rate, data bits, parity, and

stop bits.

The transmitter shift register is an 8-bit shift register, that gets its data from the transmitter FIFO. Bit

0 of the shift register will be sent first.

10.1.5

Receiver Control

After that the receiver is enabled, the controller will be looking for the start bit on the serial input line

(RX). A “0” on serial input only will be recognized as start bit, if a “1” was detected in the bit before.

When the receive control detects a start bit, the receiving operation will start.

The output of the baud rate generator (SIOCLK) is 16 times the frequency of the data transfer rate on

serial interface. The serial data input (RX) will be sampled on 7

th, 8th and 9th clock of SIOCLK. A

majority logic determines the input value.

The receiver shift register consists of an 8-bit shift register. At the end of a transmission, bit 0 of the

shift register contains the bit which has been received first.

10.1.6

Host Interface

The data transfer to the transmitter FIFO can be handled via interrupt processing or via DMA

transfer. If the transmitter FIFO has as many free entries as set in the transmit DMA interrupt trigger

level (TDIL in FIFO control register), an interrupt or DMA request is generated. Afterwards the DMA

Controller or the software fetches data from memory and writes it to the transmitter FIFO.

The data transfer from the receiver FIFO can be handled via polling, interrupt processing or via DMA

transfer. If the receiver FIFO has as much free space as set in the receive DMA interrupt trigger level

(RDIL in FIFO control register), an interrupt or DMA request is generated. Afterwards the DMA

Controller or the software fetches data from the receive FIFO and writes it to memory.

TMPR3916 Datasheet(PDF) 180 Page - Toshiba Semiconductor

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