TMPR3916 datasheet(188/225 Pages) TOSHIBA

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Chapter 10 Asynchronous Serial Interface (UART)

Preliminary

10-13

Bit

Name

Function

Reset

Value

R/W

SPIR

Special Interrupt Request

0 = No interrupt when errors occur

1 = Send SIOEXC interrupt, when errors occur

R/W

10:9

CTSAC

CTSS Status Active Condition

Sets condition of CTS.

00 = Disable CTS

01 = CTS terminal rising edge

10 = CTS terminal falling edge

11 = Both edges

R/W

8:6



Wired to zero

SIOE

Special Interrupt on Overrun Error

0 = No actions on overrun error

1 = When an overrun error occurs, send SIOEXC interrupt and set

STIS bit in Interrupt Status Register (SIDISR)

R/W

SICTS

Special Interrupt on Receive of CTS

0 = No actions on CTS

1 = When receiving CTS, send SIOEXC interrupt and set STIS bit in

Interrupt Status Register (SIDISR)

R/W

SIBRK

Special Interrupt on Break of UART Transfer

0 = No actions on break

1 = When a break occurs, send SIOEXC interrupt and set STIS bit in

Interrupt Status Register (SIDISR)

This bit must have the same value of SIUB

R/W

SITR

Special Interrupt on Free Space in Transmit FIFO (RBRKD)

0 = No actions on free space in transmit FIFO

1 = When free space is detected, send SIOEXC interrupt and set

STIS bit in Interrupt Status Register (SIDISR)

R/W

SIAS

Special Interrupt, when all data sent

0 = No actions, when all data sent

1 = When all data sent, transmit SIOEXC interrupt and set STIS bit in

Interrupt Status Register (SIDISR)

R/W

SIUB

Special Interrupt on Break of UART Transfer (UBRKD)

0 = No actions on break

1 = When a break occurs, send SIOEXC interrupt and set STIS bit in

Interrupt Status Register (SIDISR)

This bit must have the same value of SIBRK

R/W

The SIUB and SIBRK bits have the same behavior for the Exception Interrupt, since there is only one

Break flag in the DMA/Interrupt Status Register (SIDISR). However the SIBRK masks the UART

being in break status, the SIUB masks the detection of a BREAK. Obviously as soon as a Break is

detected (if any of the two is unmasked) the UART will send an Interrupt Request. To know if a Break

has already occurred or is still active refer to the Status Change Register (SISCIR). Setting these two

bits to 1 or 0 will not affect the behavior of the Status Change Register.

TMPR3916 Datasheet(PDF) 188 Page - Toshiba Semiconductor

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