TMPR3916 datasheet(192/225 Pages) TOSHIBA

192 / 225 page

Chapter 10 Asynchronous Serial Interface (UART)

Preliminary

10-17

10.2.7

Flow control register (SIFLCR)

Bit

Name



Bit

1514

131211

Name



RCS

TRS



RTSSC

RSDR

Bit

543

210

Name

TSDR



RTSTL

TBRK

Bit

Name

Function

Reset

Value

R/W

31:13



Wired to zero

RCS

RTS Control Select

Selects the method to control the RTS terminal.

0 = Software control

1 = Software or hardware control

R/W

TRS

Tx Request Select

Selects the transmit request.

0 = Control by transmit serial data request (TSDR).

1 = Control by transmit request command or the CTS terminal

(hardware control)

R/W



Wired to zero

RTSSC

RTS Software Control

Determines the output of the RTS terminal.

0 = Sets the RTS terminal to 0

1 = Sets the RTS terminal to 1

R/W

RSDR

Receive Serial Data Request

0 = Received data will stored

1 = Received data will not be written into FIFO

R/W

TSDR

Transmit Serial Data Request

0 = Transmission runs

1 = Halts transmission.

A running transmission will be finished.

R/W

6:2



Wired to zero

RTSTL

RTS Trigger Level

Sets the RTS hardware control assert level at the number of receive

data entries in the receiver FIFO.

Possible settings: 01, 10

R/W

TBRK

Transmitter Break

0 = Normal operation

1 = Transmit a break

R/W

When the RSDR bit is set to 1, received data will be ignored: it will not be written into FIFO. Frame,

Overrun and parity errors will not be generated.

TMPR3916 Datasheet(PDF) 192 Page - Toshiba Semiconductor

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