TMPR3916 datasheet(191/225 Pages) TOSHIBA

191 / 225 page

Chapter 10 Asynchronous Serial Interface (UART)

Preliminary

10-16

10.2.6

FIFO control register (SIFCR)

Bit

Name



Bit

1514

131211

Name

SWRST



RDIL

Bit

543

210

Name

RDIL



TDIL

TFRST

RFRST

FRSTEW

Bit

Name

Function

Reset

Value

R/W

31:16



Wired to zero

SWRST

Software Reset

0 = Normal operation

1 = Softreset of UART

This software reset lasts for 4 clock cycles. The channel will not react

to any requests during this time period.

Warning: While using instruction cache of TX39 the following

problem occurs: As it takes about 5 clock cycles to activate

software reset this might affect the next write action to a

Solution: Insert other instructions between resetting command and

next write command of the same channel.

14:9



Wired to zero

8:7

RDIL

Receive DMA/Interrupt trigger level

These bits determine at which fill level of the receive FIFO the UART

sends an interrupt or DMA request.

00 = If 1 byte in receive FIFO make a request

01 = If 2 bytes in receive FIFO make a request

others = invalid setting

R/W

6:5



Wired to zero

4:3

TDIL

Transmit DMA/Interrupt trigger level

These bits determine at which fill level of the transmit FIFO the UART

sends an interrupt or DMA request.

00 = If 1 byte in transmit FIFO make a request

01 = If 2 bytes in transmit FIFO make a request

others = Invalid setting

R/W

TFRST

Transmit FIFO Reset

0 = Normal operation

1 = Reset of transmit FIFO (only when FRSTEW = 1)

R/W

RFRST

Receive FIFO Reset

0 = Normal operation

1 = Reset of receive FIFO (only when FRDTEW = 1)

R/W

FRSTEW

FIFO Reset Enable

0 = Resets of receive and transmit FIFO are inhibited

1 = Resets of receive and transmit FIFO are possible

R/W

To properly reset the Receiver or the Transmitter FIFO, bit FRSTEW has to be set to 1 together and

at the same time in which TFRST or RFRST are set to 1. E.g.: to reset the Receiver FIFO value

0x00000003 must be written. This operation will reset the Receiver FIFO until either RFRST or

FRSTEW are set to 0 again by writing in the SIFCR register

To perform a software reset, the value of the FRSTEW bit is meaningless.

TMPR3916 Datasheet(PDF) 191 Page - Toshiba Semiconductor

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